Features
- True parallel bit-error-rate measurement across 8 lanes – SV1C-12 up to 12.5Gbps
- Fully synthesized integrated jitter injection on all lanes
- Fully automated integrated jitter testing on all lanes
- Optimized pattern generator rise-time for receiver stress test applications
- Flexible pre-emphasis and equalization
- Flexible loopback support per lane
- Hardware clock recovery per lane
- State of the art programming environment – Our Award Winning Pinetree™ development environment
- Integrated device control through SPI, I2C, or JTAG
Applications
- Parallel PHY validation of serial bus standards
- Interface test of electrical/optical media such as Backplanes, Cables, Pluggables: CFP, SFP, SFP+
- Plug-and-play system-level validation
- Timing verification: • PLL transfer function measurement • Clock recovery bandwidth verification • Frequency ppm offset characterization
- Mixed-technology applications: • High-speed ADC and DAC (JESD204) data capture and/or synthesis • FPGA-based system development • Channel and device emulation
- Clock-recovery triggering for external oscilloscope or BERT equipment